A prior approach to masking a clock signal in an integrated circuit is illustrated in FIG. 1. In FIG. 1, microprocessor 100 comprises cache unit 101 and execution unit 102. Both cache unit 101 and execution unit 102 are responsive to clock signal 103, i.e. both contain synchronous circuitry that is clocked by clock signal 103 or a clock signal derived from clock signal 103. More specifically, the synchronous logic in cache unit 101 is clocked directly with clock signal 103, and the synchronous logic in execution unit 102 is clocked with clock signal 104, which is derived from clock signal 103 through AND gate 105. AND gate 105 masks clock signal 103 by holding clock signal 104 low whenever active low clock mask signal 106 is asserted.
One advantage of using clock mask signal 106 to mask clock 103 is that a significant reduction in power consumption can be realized by causing clock mask signal 106 to be asserted when there is no need for execution unit 102 to be continuously clocked, such as when microprocessor 100 is idle. However, even when there is no need for execution unit 102 to be continuously clocked, cache unit 101 is continuously clocked so that cache unit 101 is ready to respond to a cache snoop request.
Therefore, in this prior approach to masking a clock signal in a integrated circuit, clock signal 103 is never masked as an input to cache unit 101, even though the masking of clock signal 103 into cache unit 101 would result in a further reduction in power consumption. If this prior approach to masking a clock signal is applied to cache unit 101, such that cache unit 101 is clocked with clock signal 104, then execution unit 102 would be unnecessarily clocked when cache unit 101, but not execution unit 102, must be ready to respond to a cache snoop request. Therefore, to allow clock signal 103 to be masked as an input to cache unit 101, a novel approach to masking a clock signal in an integrated circuit is desired.